The influence of the cell geometry in the programming and erasing characteristics of a fully CMOS compatible single-poly non-volatile memory cell for low cost embedded applications was investigated using cells fabricated in a standard CMOS 0.35µm-technology with transistor sizes varying form 10µm/0.3µm to 0.7µm/0.3µm, being the 0.7µm-wide cells the smallest single poly non-volatile memory cells reported until now. In addition to this, the impact of transistor separation is presented and discussed,together with the impact of the cell dimensions in the characteristics and endurance of the cells.
